1. Field of the Invention
This invention relates to a planarization method before metallization, and more particularly to a planarization method on an embedded dynamic random access memory (DRAM) before metallization.
2. Description of Related Art
FIGS. 1A-1C are cross-sectional views schematically illustrating a metallization flow of a conventional embedded DRAM. In FIG. 1, an embedded DRAM usually includes a memory region 102 and a logic region 104 on a semiconductor substrate 100. The memory region 102 includes a metal-oxide semiconductor (MOS) transistor 106 and a capacitor 108. The capacitor 108 is electrically coupled to the MOS transistor 106 at one of its two interchangeable source/drain regions 110. The logic region 104 includes a MOS transistor 112 with its two interchangeable regions 114.
Before a metallization process on the substrate 100 is carried out, an inter-layer dielectric (ILD) layer 116 must be deposited over the substrate 100 to isolate the capacitor 108. Because of the capacitor 108 structure, the difference in height on the ILD layer 116, between the memory region 102 and the logic region 104, can be as large as 9000 .ANG.. This large difference in height can cause difficulties in forming a contact window/plug in subsequent fabrication processes and results in a more complicated fabrication process.
In order to reduce the large difference in height, a chemical mechanical polishing (CMP) process is performed on the ILD layer 116 to planarize it as shown in FIG. 1B. After CMP, the ILD layer 116 becomes an ILD layer 116a with a difference in height of 4000-5000 .ANG. between the memory region 102 and the logic region 104. Even so, the difference in height is still excessive and the CMP could induce the problem known as dishing phenomenon. Referring to FIG. 1C, after CMP is completed a contact window/plug 118a is formed in the memory region 102. Then a metal layer 120a is formed, and coupled to one of two interchangeable source/drain regions 110 through the contact window/plug 118a. Similarly, in the logic region, a metal layer 120b is coupled to one of two interchangeable source/drain regions 114 through a contact window/plug 118b.
As described above, the conventional planarization on the embedded DRAM has the large difference in height between the memory region 102 and the logic region 104. The large difference in height causes difficulties in the subsequent fabrication process.